Electrostatic discharge protection circuit

ABSTRACT

An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates in general to a transistorstructure for an electrostatic discharge (ESD) protection circuit and,more particularly, to an ESD protection device having improvedperformance.

[0003] 2. Description of the Related Art

[0004] Metal oxide semiconductor (MOS) integrated circuits (ICs) receiveinput signals through the gate of a MOS transistor. If a high voltageinput signal is applied to the gate terminal, the gate oxide layer maybe unable to withstand the high voltage and break down. Higher thannormal input voltages may be produced when semiconductor devices aretransported by humans or machines. However, the sources of abnormallyhigh voltages are many. For example, electric charges can be produced byfriction between surfaces or when an IC is unpacked from plasticpackaging. Static electricity can range from several hundreds volts toseveral thousand volts. If such high voltages are applied to the pins ofan IC package, voltage breakdown of the gate oxide layer of a transistorwithin the package can occur which would result in the transistor beinginoperative. As a result, the entire IC could be rendered inoperative.

[0005] To prevent such damages to the MOS transistors, protectivecircuits are connected to pins of an IC package. Such protectivecircuits are typically connected between each input/output (I/O) pad andthe integrated circuit. The protective circuits are designed to conductwhen a high voltage is applied to the I/O pad. Hence, these protectivecircuits provide an electrical path to, e.g., ground, to safelydischarge the high voltage.

[0006] As feature sizes of semiconductor IC devices are reduced to thesub-micron level, one of the design rules for making high-speed ICs isto use self-aligned suicide (salicide) fabrication procedures to makeMOS transistor components. The goal is to effectively reduce the sheetresistance in the source/drain regions, so that the fabricated MOStransistors operate at higher speeds. However, the use of salicides forhigh-speed device circuits results in the problem of maintainingadequate ESD protection for such circuits in these IC devices. If theESD protection circuits are also implemented in the same salicidefabrication technology, then the sheet resistance in the N+ diffusionregions for the ESD protection circuits will fall from the traditionalrange of about 60 Ω per-square for effective protection to about 2-3 Ωper-square.

[0007]FIG. 1 is a reproduction of FIG. 4 of U.S. Pat. No. 5,742,083which illustrates the layout of an ESD protection circuit. The ESDcircuit shown in FIG. 1 includes an MOS transistor that includes fieldoxide islands 40 a-40 g that extend from a drain diffusion region 42 inthe transistor drain side into the source side. Field oxide islands 40a-40 g pass underneath a strip-shaped gate structure 41, but do notextend to a metallization overlying and connected to the drain diffusionregion via contact openings 43 a-43 g. Islands 40 a-40 g serve tosegment part of drain diffusion region 42, into segmented regions 42a-42 g, across which current flows during an ESD event. This arrangementserves to partially distribute current during an ESD event which canimprove ESD protection.

[0008] While the arrangement in FIG. 1 provides some improvement in ESDprotection, further improvement is desirable.

SUMMARY OF THE INVENTION

[0009] Accordingly, the present invention is directed to an ESDprotection device that substantially obviates one or more problems dueto limitations and disadvantages of the related art.

[0010] Additional features and advantages of the invention will be setforth in the description which follows, and in part will be apparentfrom the description, or may be learned by practice of the invention.The objectives and advantages of the invention will be realized andattained by means of the elements and combinations particularly pointedout in the written description and claims hereof, as well as theappended drawings. To achieve these and other advantages and inaccordance with the purpose of the invention, as embodied and broadlydescribed, there is provided an electrostatic discharge protectiondevice, comprising: a substrate; a first diffusion region formed in thesubstrate; a second diffusion region formed in the substrate adjacent toand spaced from the first diffusion region; contacts for making aconductive connection to the first diffusion region; a channel formed ina third region between the first and second diffusion region; and anelongate current divider extending between the channel and a region ofthe contacts.

[0011] Also in accordance with the present invention, there is providedan electrostatic discharge protection device, comprising: a substrate; afirst diffusion region formed in the substrate; a second diffusionregion formed in a spaced relationship to the first diffusion region; athird diffusion region formed in the substrate between and spaced fromthe first and second diffusion regions; a first gate overlying a regionbetween the first and third diffusion regions; a second gate overlying aregion between the second and third diffusion regions; contacts formaking a conductive connection to the third diffusion region; a firstelongate current divider extending between the first gate and a regionof the contacts; and a second elongate current divider extending betweenthe second gate and the region of the contacts.

[0012] Further in accordance with the present invention, there isprovided an electrostatic discharge protection device, comprising: asubstrate; a first diffusion region formed in the substrate; a seconddiffusion region formed in the substrate adjacent to and spaced from thefirst diffusion region; contacts for making a conductive connection tothe first diffusion region; a channel formed in a third region betweenthe first and second diffusion region; a first elongate current dividerextending between the channel and a region of the contacts; and a secondelongate current divider adjacent to the first divider and extendingbetween the channel and a region of the contacts.

[0013] Additionally in accordance with the present invention, there isprovided an electrostatic discharge protection device, comprising: asubstrate; a first diffusion region formed in the substrate; a seconddiffusion region formed in a spaced relationship to the first diffusionregion; a third diffusion region formed in the substrate between andspaced from the first and second diffusion regions; a first gateoverlying a region between the first and third diffusion regions; asecond gate overlying a region between the second and third diffusionregions; contacts for making a conductive connection to the thirddiffusion region; a plurality of adjacent first elongate currentdividers extending between the first gate and a region of the contacts;and a plurality of adjacent second elongate current dividers extendingbetween the second gate and the region of the contacts.

[0014] Further in accordance with the present invention, there isprovided an electrostatic discharge protection device, comprising: asubstrate; a first diffusion region formed in the substrate; a seconddiffusion region formed in the substrate adjacent to and spaced from thefirst diffusion region; contacts for making a conductive connection tothe first diffusion region; a channel formed in a third region betweenthe first and second diffusion regions; and a plurality of currentdivider segments formed within the first diffusion region, therespective segments each formed into one of at least two differentshapes, two different sizes, or two different orientations.

[0015] Additionally in accordance with the present invention, there isprovided an electrostatic discharge protection device, comprising: asubstrate; a first diffusion region formed in the substrate; a seconddiffusion region formed in the substrate adjacent to and spaced from thefirst diffusion region; contacts for making a conductive connection tothe first diffusion region; a channel formed in a third region betweenthe first and second diffusion regions; and a plurality of small currentdivider segments formed within the first diffusion region and being oneof evenly and unevenly distributed therein.

[0016] Also in accordance with the present invention, there is providedan electrostatic discharge protection device, comprising: a substrate; afirst diffusion region formed in the substrate; a second diffusionregion formed in the substrate adjacent to and spaced from the firstdiffusion region; contacts for making a conductive connection to thefirst diffusion region; a channel formed in a third region between thefirst and second diffusion regions; and a plurality of current dividersegments formed within the first diffusion region and being unevenlydistributed therein.

[0017] Further in accordance with the present invention, there isprovided a method for forming an electrostatic discharge protectiondevice, comprising the steps of: forming a substrate; forming a firstdiffusion region formed in the substrate; forming a second diffusionregion in the substrate adjacent to and spaced from the first diffusionregion; forming contacts for making a conductive connection to the firstdiffusion region; forming a channel in a third region between the firstand second diffusion region; and forming an elongate current dividerextending between the channel and a region of the contacts.

[0018] It is to be understood that both the foregoing generaldescription and the following detailed description are exemplary andexplanatory only and are not restrictive of the invention, as claimed.

[0019] The accompanying drawings are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification, illustrate embodiments of the invention, andtogether with the description serve to explain principles of theinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020]FIG. 1 illustrates a portion of a prior art ESD protection device;

[0021] FIGS. 2A-2D illustrate an ESD protection device constructedaccording to a first embodiment of the present invention;

[0022]FIGS. 3A and 3B illustrate an ESD protection device thatrepresents an alternate construction of the device illustrated in FIGS.2A-2D;

[0023]FIGS. 4A and 4B illustrate an ESD protection device thatrepresents another alternate construction of the device illustrated inFIGS. 2A-2D;

[0024]FIGS. 4C and 4D illustrate an ESD protection device thatrepresents another alternate construction of the device illustrated inFIGS. 2A-2D.

[0025]FIG. 5 illustrates an ESD protection device that represents yetanother alternate construction of the device illustrated in FIGS. 2A-2D;

[0026]FIG. 6 is a plan view of an ESD protection device configured as aGGNMOS;

[0027]FIGS. 7A and 7B illustrate an ESD protection device constructedaccording to a second embodiment of the present invention, and FIG. 7Cillustrates a plan view of an alternate construction of that device;

[0028] FIGS. 8A-8C illustrate an ESD protection device constructedaccording to a third embodiment of the present invention;

[0029]FIG. 9 illustrates a plan view of an ESD protection device thatrepresents an alternate construction of the device illustrated in FIGS.8A-8C;

[0030] FIGS. 10A-10C illustrate an ESD protection device constructedaccording to a fourth embodiment of the present invention;

[0031] FIGS. 11A-11D illustrate an ESD protection device constructedaccording to a fifth embodiment of the present invention;

[0032] FIGS. 12A-12C illustrate an ESD protection device constructedaccording to a sixth embodiment of the present invention;

[0033]FIG. 13 illustrates an ESD protection device constructed accordingto a seventh embodiment of the present invention;

[0034]FIG. 14 illustrates an ESD protection device constructed accordingto a eighth embodiment of the present invention;

[0035]FIG. 15 illustrates an ESD protection device constructed accordingto a ninth embodiment of the present invention;

[0036]FIG. 16 illustrates an ESD protection device constructed accordingto a tenth embodiment of the present invention;

[0037]FIG. 17 illustrates an ESD protection device constructed accordingto a eleventh embodiment of the present invention;

[0038]FIG. 18 illustrates an ESD protection device constructed accordingto a twelfth embodiment of the present invention;

[0039]FIG. 19 illustrates an ESD protection device constructed accordingto a thirteenth embodiment of the present invention;

[0040]FIG. 20 illustrates an ESD protection device constructed accordingto a fourteenth embodiment of the present invention;

[0041]FIG. 21 illustrates an ESD protection device constructed accordingto a fifteenth embodiment of the present invention;

[0042]FIG. 22 illustrates an ESD protection device constructed accordingto a sixteenth embodiment of the present invention;

[0043]FIG. 23 illustrates an ESD protection device constructed accordingto an seventeenth embodiment of the present invention;

[0044]FIG. 24 illustrates an ESD protection device constructed accordingto an eighteenth embodiment of the present invention;

[0045]FIG. 25 illustrates an ESD protection device that represents analternate construction of the device illustrated in FIG. 24; and

[0046]FIG. 26 illustrates an ESD protection device that representsanother alternate construction of the device illustrated in FIG. 24.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0047] Embodiments consistent with the present invention comprise anMOSFET ESD protection device that includes current divider structuresthat at least partially divide current flow through the drain regionduring an ESD event. The current divider structures also increaseimpedance in the current flow path. A more evenly distributed currentflow during the ESD event resulting from the divided current flow, aswell as the increased impedance, result in the ESD device providingimproved ESD voltage tolerance.

[0048] Throughout this description, like features are identified withthe same reference numerals.

[0049] FIGS. 2A-2D illustrate an ESD protection device 200 according toa first embodiment of the present invention. FIGS. 2B, 2C, and 2Dillustrate sections 2B-2B, 2C-2C, and 2D-2D indicated in FIG. 2A, whichis a top view of device 200. Device 200 20 is formed within an activeregion 201 which is defined by, e.g., a surrounding field oxide. Device200 can be formed in a p-well or p-type silicon substrate 202 and isisolated from adjacent devices by field oxide regions 204 and n-wellregions 206. An N+ source region 208 and an N+drain region 210 areformed in substrate 202. An elongate polysilicon gate 212 is disposedover a thin gate oxide 214 between regions 208 and 210. A channel region216 is disposed under gate 212 and oxide 214. Oxide spacers 215 areformed on sides of gate 212. Metal bus layer 218 overlies sourcediffusion region 208 and is connected thereto by source contacts 220. Ametal bus layer 222 overlies drain diffusion region 210 and is connectedthereto by contacts 224. Layer 222 is an anode of device 200. Theconnections to regions 208 and 210 are shown diagrammatically in FIGS.2B and 2C. The source and drain regions are typically heavily doped byion implantation, followed by thermal diffusion at elevated temperatureprocessing steps. Therefore, a source or drain region can be called aheavily doped region or a diffusion region.

[0050] A P+ region 230 is formed in substrate 202. Layer 218 isconnected to region 230 by contacts 232. Region 230 serves as a guardring that surrounds active region 201 and is spaced therefrom by a fieldoxide 231. Region 230 facilitates a low resistance connection tosubstrate 202. Drain region 210 can be coupled through layer 222 to aninput, output, I/O pad or a first power bus, e.g., a VDD bus, 234.Source region 208 can be coupled through layer 218 to a second powerbus, e.g., a Vss bus, 236. Gate 212 can be coupled directly to layer218, i.e., the cathode, to form a grounded gate NMOS (GGNMOS)transistor, be coupled to layer 218 through a resistor (not shown), becoupled to layer 222, i.e., the anode, through a capacitor (not shown),or be coupled to a gate-driving signal. A terminal 238 is shown in FIG.2A as connected to gate 212 to diagrammatically represent the variousconnection options for gate 212.

[0051] Device 200 further includes an array of elongate current dividersegments 240 formed within drain region 210. Each segment 240 is formedof a field oxide. The space between adjacent segments 240 is greaterthan the width of each segment 240. For example, the space betweenadjacent segments 240 can be approximately two times the width of eachsegment 240. Alternatively, the space between adjacent segments can begreater, e.g., four times the segment width. As seen in FIGS. 2A-2C,segments 240 are disposed between gate 212 and layer 222 but do notextend beneath either of gate 212 or layer 222. Segments 240 arepreferably evenly spaced from each other and across a width of drainregion 210.

[0052]FIGS. 3A and 3B illustrate an ESD protection device 300 thatrepresents an alternate construction of device 200. Device 300 isconfigured the same as device 200 except that device 300 is formed withsilicon-on-insulator (SOI) process technology. FIGS. 3A and 3Billustrate cross-sectional views of device 300 that correspond tosections 2B-2B and 2D-2D of device 200, respectively. Device 300includes a silicon substrate 302 and an insulator or implanted oxidelayer 304 formed on substrate 302. Device 300 includes a p-well 306 thatcorresponds to substrate 202 and underlies gate 212 and segments 240.

[0053]FIGS. 4A and 4B illustrate an ESD protection device 400 thatrepresents another alternate construction of device 200. Device 400 isconfigured the same as device 200 except that device 400 includes anarray of elongate current divider segments 402 that are each formed of apolysilicon layer 404 over a thin oxide layer 406, instead of fieldoxide segments 240. Each segment 402 also includes oxide spacers 408surrounding its periphery. FIGS. 4A and 4B illustrate cross-sectionalviews of device 400 that correspond to sections 2B-2B and 2D-2D ofdevice 200, respectively.

[0054]FIGS. 4C and 4D illustrate an ESD protection device 450 thatrepresents yet another alternate construction of device 200. Device 450is configured the same as device 200 except that device 450 includes anarray of elongate current divider segments 452 that are each formed offield oxide overlayed by polysilicon. FIGS. 4C and 4D illustratecross-sectional views of device 450 that correspond to sections 2B-2Band 2D-2D of device 200, respectively. As seen in FIGS. 4C and 4D, eachsegment includes a field oxide layer 454 disposed on substrate 202 and apolysilicon layer 456 disposed over layer 454. The periphery of layer456 extends beyond the edge of layer 454. A thin oxide 458 is disposedbetween that peripheral portion of layer 456 and substrate 202.Optionally, a connection 460 can be provided to layer 456 for connectionto, e.g., ground, gate 212, or drain contact 224, at a designer'sdiscretion. Existence of the underlying field oxide layer 454 which isthick relative to a typical gate oxide, enhances the ability to form ametal contact directly on polysilicon on field oxide for makingconnection 460 to layer 456.

[0055]FIG. 5 illustrates an ESD protection device 500 that representsyet another alternate construction of device 200. Device 500 isconfigured the same as device 200 except that device 500 is both formedwith SOI process technology and with current divider segments 402 formedof polysilicon layer 404 over oxide layer 406.

[0056] In each of devices 200, 300, 400, and 500, the elongate currentdivider segments serve to segment or divide drain region 210 into aplurality of parallel current paths. The manner in which thisarrangement of the current divider segments enhances ESD protectionperformance is described more fully below.

[0057]FIG. 6 is a plan view of an ESD protection device 600 thatrepresents an implementation of the configuration of device 200 in amulti-gate-finger GGNMOS. Thus, device 600 includes a plurality ofpolysilicon gates 212 respectively connected to a polysilicon or metalinterconnect 602. Rectangle 604 defines an active region, surrounded byfield oxide, within which device 600 is formed. Device 600 includes aplurality of source regions 208 and drain regions 210 with each gate 212disposed between a pair of regions 208 and 210. Contacts 220 provideconnections to each source region 208 and contacts 224 provideconnections to each drain region 210. Device 600 includes metal buslayers, not shown, that contacts 220 and 224 connect to. A plurality offield oxide current divider segments 240 are formed within each of drainregions 210.

[0058]FIGS. 7A and 7B illustrate an ESD protection device 700 accordingto a second embodiment of the present invention. FIG. 7A is a plan viewof device 700 and FIG. 7B illustrates section 7B-7B indicated in FIG.7A. Device 700 comprises the same features as device 200, except thatone end of each current divider segment 240 extends partially underneathpolysilicon gate 212. As illustrated in FIG. 7B, thin gate oxide 214 isonly disposed on substrate 202, while gate 212 overlies both oxide 214and an end of each segment 240.

[0059]FIG. 7C illustrates a plan view of an ESD protection device 750that represents an alternate construction of device 700. In particular,device 750 includes field oxide current divider segments 752 thatinclude a relatively narrow segment portion 754 that extends partiallyunderneath polysilicon gate 212 and a relatively wider segment portion756 that extends within drain region 210. The use of segments 752 isefficacious in devices formed by salicide or silicided diffusionprocesses because the wider segment portions 756 serve to narrow currentpaths and thereby increase drain resistance for improved ESDperformance. Further, since the effect of providing wider segmentportions 756 is to increase drain resistance, each field oxide segmentcan instead be configured with at least some portion of its lengthhaving an increased width to provide a narrowed portion of current pathin the drain region.

[0060] FIGS. 8A-8C illustrate an ESD protection device 800 according toa third embodiment of the present invention. FIG. 8A is a plan view ofdevice 800, while FIGS. 8B and 8C are sections 8B-8B and 8C-8C indicatedin FIG. 8A. The features of device 800 are arranged similarly tocorresponding features of device 200, including the spacing of currentdivider segments 240 away from gate 212. However, device 800additionally includes gate extensions 802 that respectively extend fromgate 212 and overlies an end portion of each segment 240.

[0061]FIG. 9 illustrates a plan view of an ESD protection device 900that represents an alternate construction of device 800. In device 900,each current divider segment 240 extends underneath polysilicon gate212, while gate extension 902 extends from gate 212 and overlies aportion of each segment 240.

[0062] FIGS. 10A-10C illustrate an ESD protection device 1000 accordingto a fourth embodiment of the present invention. FIG. 10A illustrates aplan view of device 1000 while FIGS. 10B and 10C illustrate sectionalviews 10B-10B and 10C-10C indicated in FIG. 10A. Device 1000 includescurrent divider segments 1002 each formed of a polysilicon layer 1004over a thin oxide layer 1006. Each segment 1002 is contiguous with andextends substantially perpendicularly from gate 212. Thus, as shown inFIGS. 10A and 10B polysilicon layer 1004 is contiguous with thepolysilicon of gate 212 and oxide layer 1006 is contiguous with oxidelayer 214.

[0063] FIGS. 11A-11D illustrate an ESD protection device 1100 accordingto a fifth embodiment of the present invention. FIG. 11A illustrates aplan view while FIG. 11B illustrates sectional view 11B-11B indicated inFIG. 11A. FIGS. 11C and 11D illustrate sectional view 11X-11X indicatedin FIG. 11A and respectively correspond to alternate constructions ofdevice 1100. Device 1100 includes a stripe of field oxide 1102 insteadof a polysilicon gate between source region 208 and drain region 210.Field oxide 1102 overlies a channel region 1104 in substrate 202. Device1100 also includes elongate current divider segments 1106 formed withindrain region 210. Segments 1106 can be configured to have the samelength and spacing as discussed above for segments 240 of device 200.Segments 1106 can be formed of field oxide segments 1108 as shown inFIG. 11C or as polysilicon segments 1110 as shown in FIG. 11D. Eachpolysilicon segment 1110 includes a polysilicon layer 1112 over a thinoxide layer 1114.

[0064] Device 1100 is configured as an NPN bipolar device with sourceregion 208 and drain region 210 corresponding to the emitter andcollector, respectively, and substrate 202 corresponding to the base.When used for ESD protection, the collector serves as the anode and theemitter serves as the cathode. As described above, the anode can beconnected to an input, output, I/O pad or a first power bus, while thecathode can be coupled to a second power bus.

[0065] While region 230 is not explicitly shown in FIGS. 7A, 7C, 8A, 9,1A, and 11A, it is typically included, such as shown in sectional views7B, 8B, 8C, 10B, 10C, and 11B-11D.

[0066] FIGS. 12A-12C illustrate an ESD protection device 1200 accordingto a sixth embodiment of the present invention. FIG. 12A illustrates aplan view, while FIGS. 12B and 12C illustrate sectional views 12B-12Band 12C-12C indicated in FIG. 12A. Device 1200 includes a stripe offield oxide 1202 instead of a polysilicon gate between source region 208and drain region 210. Field oxide 1202 overlies a channel region 1204 insubstrate 202. Device 1200 also includes elongate current dividersegments 1206 each formed of field oxide. Each segment 1206 iscontiguous with and extends substantially perpendicularly from oxide1202.

[0067] Device 1200, like device 1100, is configured as an NPN bipolardevice with source region 208 and drain region 210 corresponding to theemitter and collector, respectively, and substrate 202 corresponding tothe base.

[0068] FIGS. 13-23 illustrate further embodiments of ESD protectiondevices constructed according to the present invention. Each of thedevices illustrated in FIGS. 13-23 include two gates, or gate fingers,connected to and extending from a polysilicon or metal interconnect. Inpractice, such devices would preferably be constructed to include aneven number of gates, e.g., 2, 4, 6, etc., gates, with a common drainregion between each pair of gates and the outermost portions of thediffusion region adjacent the outermost gates serving as source regions.Device 600 in FIG. 6 is an example of such a multigate configuration.The ESD protection devices 200-1000 while illustrated as each containinga single gate can also be implemented with a multiple gate architecture.Such devices are useful as ESD protection devices with either a singlegate or multiple gate architecture.

[0069]FIG. 13 illustrates an ESD protection device 1300 according to aseventh embodiment of the present invention. Device 1300 is formed in ap-type silicon substrate 1302 and includes a region 1304 in which areformed N+source diffusion regions 1306 and 1308 and an N+drain diffusionregion 1310. Region 1304 defines the boundaries of the source and draindiffusion regions. Region 1304 is surrounded by a field oxide (notshown). Polysilicon gates 1312 and 1314 are interconnected by apolysilicon or metal interconnect 1316. Gate 1312 is positioned over achannel region between diffusion regions 1306 and 1310 and gate 1314 ispositioned over a channel region between diffusion regions 1308 and1310. Metal bus layers 1318 and 1320 respectively overlie sourcediffusion regions 1306 and 1308 and are connected thereto by sourcecontacts 1322. A metal bus layer 1324 overlies drain diffusion region1310 and is connected thereto by drain contacts 1326.

[0070] Device 1300 is connected between an anode 1328 and a cathode1330. Anode 1328 is connected to metal layer 1324 and cathode 1330 isconnected to metal layers 1318 and 1320. Anode 1328 can, in turn, becoupled to an input, output, I/O pad, or a first power bus. Cathode 1328can be coupled to another IC pad or to a second power bus, e.g., to areference or ground bus.

[0071] Device 1300 further includes a row of elongate polysiliconcurrent divider segments 1332 and a row of elongate polysilicon currentdivider segments 1334. Each segment 1332 is formed within draindiffusion region 1310 and extends between gate 1312 and the region ofdrain contacts 1326 and under metal layer 1324. Similarly, each segment1334 is formed within drain diffusion region 1310 and extends betweengate 1314 and the region of contacts 1326. Further, one end of eachsegment 1332 is connected to gate 1312 and one end of each segment 1334is connected to gate 1314. These connections are achieved by forminggates 1312 and 1314 and segments 1332 and 1334 in the same processsteps. The opposite end of each of segments 1332 and 1334 terminateswithin the drain-side active region and spaced from drain contacts 1326.

[0072] Each of segments 1332 is skewed relative to gate 1312 at an acuteangle Θ₁ of, for example, 30°, 45°, or 60°. Segments 1332 are preferablyall skewed at the same angle so they are parallel to each other.Similarly, each of segments 1334 is skewed relative to gate 1314 at anacute angle Θ₂ which is, preferably, the same as the angle Θ₁, at whichsegments 1332 are skewed. Optionally, segments 1332 can be uniformlyspaced and segments 1334 are disposed in a one-to-one correspondencewith segments 1332. As another option, the respective skews of segments1330 and 1332 can be oriented relative to gate 1312 and 1314 so that thearrangement of segments of 1332 is symmetrical with respect to thearrangement of segments 1334.

[0073] During an ESD event, with segments 1332 and 1334 arranged asdescribed above, each adjacent pair of segments 1332 or 1334 defines acurrent path for current flow between source contacts 1320 and draincontacts 1326.

[0074]FIG. 14 illustrates an ESD protection device 1400 according to aeighth embodiment of the present invention. With reference FIG. 14,device 1400 differs from device 1300 by inclusion of field oxidesegments 1402 that respectively interconnect corresponding pairs ofsegments 1332 and 1334. Each segment 1402 is formed in drain diffusionregion 1310 and is positioned between adjacent drain contacts 1326. As aresult, each connected set of corresponding segments 1332 and 1334 andsegment 1402 forms a single current divider structure 1404. Further,each pair of adjacent current divider structures 1404 defines a currentpath for current flow between source contacts 1322 and drain contacts1326 during an ESD event. Structures 1404 therefore fully segment drainregion 1310. Use of field oxide segment 1402 to join segments 1332 and1334 instead of a polysilicon segment on thin oxide segment, obviatesthe possibility of damage that may otherwise occur to the thin oxideresulting from high current densities and heating due to proximity todrain contacts 1326.

[0075]FIG. 15 illustrates an ESD protection device 1500 according to aninth embodiment of the present invention. Device 1500 differs fromdevice 1300 by providing a further polysilicon current divider segment1502 that connects each pair of segments 1332 and 1334 to provide acontiguous polysilicon current divider segment 1504. Since each ofsegments 1332 and 1334 is connected to gates 1312 and 1314,respectively, current divider segments 1504 fully divide drain diffusionregion 1310.

[0076]FIG. 16 illustrates an ESD protection device 1600 according to atenth embodiment of the present invention. Device 1600 includespolysilicon current divider segments 1602 that are substantiallyparallel to each other and evenly spaced across drain diffusion region1310. Each segment 1602 includes a first portion 1604 extending towardgate 1312, but not connected thereto, and a second portion 1606extending toward gate 1314, but not connected thereto. Each segment 1602extends under metal layer 1324, is insulated therefrom by a dielectriclayer (not shown) and is positioned between adjacent drain contacts1326. Each portion 1604 is skewed relative to gate 1312 by angle Θ₁ andeach portion 1606 is skewed relative to gate 1314 by angle Θ₂. Each ofΘ₁, and Θ₂ is an acute angle of, for example, 140°, 155°, or 60°.Preferably, Θ₁ is equal to Θ₂. Since each segment 1602 is not connectedto either of gates 1312 or 1314, segments 1602 partially divide draindiffusion region 1310.

[0077]FIG. 17 illustrates an ESD protection device 1700 according to aeleventh embodiment of the present invention. Device 1700 includes fieldoxide current divider segments 1702 that are substantially parallel toeach other and evenly spaced across drain diffusion region 1310. Eachsegment 1702 extends under metal layer 1324, is insulated therefrom by adielectric layer (not shown) and is positioned between adjacent draincontacts 1326. The respective ends of each segment 1702 extend towardbut are not connected to gates 1312 and 1314. Each segment 1702 issubstantially straight as shown in FIG. 17 and skewed relative to gates1312 and 1314 by angle Θ₁. Since each segment 1702 is not connected toeither of gates 1312 or 1314, segments 1702 partially divide draindiffusion region 1310.

[0078]FIG. 18 illustrates an ESD protection device 1800 according to atwelfth embodiment of the present invention. Device 1800 differs fromdevice 1300 by including polysilicon current divider segments 1802 and1804 that are substantially perpendicular to gates 1312 and 1314.Segments 1802 and 1804 are connected to gates 1312 and 1314,respectively. Segments 1802 and 1804 are evenly spaced across draindiffusion region 1310 and each segment 1802 aligns with an associatedsegment 1804. The free end of each segment 1802, i.e., remote from gate1312, extends into the region of drain contacts 1326 and under metallayer 1324. Similarly, the free end of each segment 1804, i.e., remotefrom gate 1314, extends into the region of drain contacts 1326 and undermetal layer 1324. Further, each pair of associated segments 1802 and1804 are positioned such that their free ends are maintained at adistance of at least 0.5 μm and, preferably 1-4.5 μm from the nearestdrain contacts 1326. As in the case of device 1300, each adjacent pairof segments 1802 or 1804 defines a current path for current flow betweensource contacts 1320 and drain contacts 1326 during an ESD event.

[0079]FIG. 19 illustrates an ESD protection device 1900 according to athirteenth embodiment of the present invention. Device 1900 includescurrent divider segments 1902 formed within drain diffusion region 1310that are substantially parallel to each other and evenly spaced acrossdrain diffusion region 1310. Each segment 1902 includes a field oxidesegment 1904 and polysilicon segments 1906 and 1908 that extend fromopposite ends of segment 1904. Each polysilicon segment 1906 isconnected to gate 1312 and each polysilicon segment 1908 is connected togate 1314. Each segment 1902 is substantially perpendicular to gates1312 and 1314 and positioned between adjacent drain contacts 1326. Eachfield oxide segment 1904 is positioned under and insulated from metallayer 1324 by a dielectric layer (not shown). Since each segment 1902extends between and is connected to gates 1312 and 1314, segments 1902fully divide drain diffusion region 1310.

[0080]FIG. 20 illustrates an ESD protection device 2000 according to anfourteenth embodiment of the present invention. Device 2000 includespolysilicon current divider segments 2002 formed within drain diffusionregion 1310 that are substantially parallel to each other and evenlyspaced across drain diffusion region 1310. The opposite ends of eachsegment 2002 are connected to gates 1312 and 1314. Each segment 2002 issubstantially perpendicular to gates 1312 and 1314 and positionedbetween adjacent drain contacts 1326. Each segment 2002 is positionedunder and insulated from metal layer 1324 by a dielectric layer (nowshown). Since each segment 2002 extends between and is connected togates 1312 and 1314, segments 2002 fully divide drain diffusion region1310.

[0081]FIG. 21 illustrates an ESD protection device 2100 according to afifteenth embodiment of the present invention. Device 2100 includespolysilicon current divider segments 2102 formed within drain diffusionregion 1310, that are substantially parallel to each other and evenlyspaced across drain diffusion region 1310. The opposite ends of eachsegment 2102 are spaced from, i.e., not connected to, gates 1312 and1314. Each segment 2102 is oriented substantially perpendicular to gates1312 and 1314 and positioned between adjacent drain contacts 1326. Eachsegment 2102 is positioned under and insulated from metal layer 1324 bya dielectric layer (not shown). Since each segment 2102 is not connectedto either of gates 1312 or 1314, segments 2102 partially divide draindiffusion region 1310.

[0082]FIG. 22 illustrates an ESD protection device 2200 according to asixteenth embodiment of the present invention. Device 2200 includesfield oxide current divider segments 2202 formed within drain diffusionregion 1310 that are substantially parallel to each other and evenlyspaced across drain diffusion region 1310. Each segment 2202 extendsunder metal layer 1324 and is insulated therefrom by a dielectric layer(not shown). Each segment 2202 is positioned between adjacent draincontacts 1326. The respective ends of each segment 2202 extend towardbut are not connected to gates 1312 and 1314. Each segment 2202 issubstantially straight as shown in FIG. 22 and oriented to besubstantially perpendicular to gates 1312 and 1314. Since each segment2202 is not connected to either of gates 1312 or 1314, segments 2202partially divide drain diffusion region 1310.

[0083]FIG. 23 illustrates an ESD protection device 2300 according to aseventeenth embodiment of the present invention. Device 2300 includesfield oxide current divider segments 2302 formed within drain diffusionregion 1310 that are substantially parallel to each other and evenlyspaced across drain diffusion region 1310. Each segment 2302 extendsunder metal layer 1324 and is insulated therefrom by a dielectric layer(not shown). Each segment 2302 is substantially straight as shown inFIG. 23 and oriented to be substantially perpendicular to gates 1312 and1314. Since each segment 2302 extends beyond gates 1312 and 1314,segments 2302 fully segment drain diffusion region 1310. Each pair ofdrain contacts 1326 can be arranged parallel to segments 2302 toincrease the spacing therefrom. This arrangement reduces currentdensities while keeping a minimum spacing between contacts 1326 andadjacent segment 2302. This minimum spacing can be 0.5 μm or larger,without degrading ESD performance.

[0084]FIG. 24 illustrates an ESD protection device 2400 according to aneighteenth embodiment of the present invention. Device 2400 includesrandomly distributed current divider segments 2402 formed within draindiffusion region 1310. Segments 2402 can be provided with a variety ofshapes including one or more of square, rectangular, circular,cross-shaped, T-shaped, V-shaped, L-shaped, U-shaped, and any other oddshapes. More generally, segments 2402 can include segments of the sameshape but of different size or orientation. The random distribution ofsegments 2402 includes their respective centers of areas being unevenlydistributed. Alternatively, the respective centers of areas can beevenly distributed or aligned while the shapes are oriented in a mannerto provide an uneven, or random, distribution. In one construction,segments 2402 are provided to all be small such that the largestdimension is less than or equal to six times the length of the channelregion, i.e., that length being substantially the distance between thesource and drain regions of an MOS transistor structure, or between theemitter and collector regions of a bipolar structure.

[0085] Each segment 2402 can be formed of polysilicon or field oxide. Inan alternate construction, gates 1312 and 1314 can be replaced withstripes of field oxide and interconnect 1316 can be eliminated.

[0086]FIG. 25 illustrates an ESD protection device 2500 that representsan alternate construction of device 2400. While device 2500 isillustrated as having a single gate, it can be constructed to have aplurality of, such as an even number of gates, as in device 2400. Device2500 differs from device 2400 in providing a plurality of small,similarly shaped current divider segments 2502 that are unevenly, orrandomly, distributed in drain diffusion region 210. The unevendistribution of segments 2502 is preferably achieved by providing randomdistances between adjacent ones of segments 2502. The largest dimensionof each of segments 2502 is less than or equal to six times the lengthof the channel region, i.e., that length being substantially thedistance between the source and drain regions. Each of segments 2502 isformed of polysilicon or field oxide.

[0087]FIG. 26 illustrates an ESD device 2600 that represents anotheralternate construction of device 2400. With reference to FIG. 26, device2600 includes groups 2602 of small current divider segments 2604 in andalong drain region 1310 adjacent to each of gates 1312 and 1314. Eacharray 2602 is disposed within region 1304 with the respective left andright ends of each array 2602 approximately equidistant from the leftand right edges, respectively, of region 1304. However, arrays 2602 canbe disposed relative to the edges of region 1304 in the same manner asillustrated in other embodiments described herein.

[0088] Device 2600 can also be alternatively provided with a pluralityof evenly, unevenly or randomly distributed segments 2604 instead ofarrays 2602 disposed along gates 1312 and 1314 in drain region 1310.

[0089] In the operation of an ESD protection device consistent with thepresent invention, current flow through the drain region is divided bythe current divider segments. This results in a more uniformdistribution of current across the drain region and increased impedancein the drain region.

[0090] During an ESD event, the high ESD voltage at the anode (drainregion) causes junction avalanche breakdown, which causes generation ofelectron-hole pairs in the n+diffusion-to-p-well junction. The electronsare collected by the anode while the holes flow in the substrate towardsthe source (cathode) junction. The hole current flow induces an IRvoltage drop in the p-well, or p-type substrate, thus causing a forwardbias between the p-well and the n+ source junction. The forward-biasedsource junction injects many electrons into the p-well. These injectedelectrons are collected by the drain junction and more electron-holepairs are generated due to high-field impact ionization in the drainjunction. This process iterates as the known snap-back characteristic ofESD current absorption while limiting the anode-to-cathode transientvoltage. In conventional devices, the high current and high field at thedrain junction near the gate generates heat and raises localtemperature, which may cause damage to the drain contacts or the gate.

[0091] Current divider segments consistent with the present inventioncreate a pseudo-collector structure in that, during snap-back, theelectrons injected from the forward-biased source junction are partiallyabsorbed by the drain junctions around the periphery of each segment.This effectively reduces the ESD current density at the drain junctionnear the gate. Also, the electric field is higher at the corners of thesegments than at the drain junction next to the gate due to acorner-electric-field-crowding effect. This higher electric field at thecorners of the segments, particularly those corners near the gate, helpsthe impact ionization process to generate more electron-hole pairs in apositive feedback to facilitate an early trigger of the snap-back duringan ESD event. For example, in device 2400 shown in FIG. 24, thecorner-electric-field-crowding effect occurs at the inside and outsidecorners of the various shapes of segments 2402. This has the effect oflowering the trigger voltage of device 2400.

[0092] The benefits of the pseudo-collector structure can be furtherenhanced by positioning the current divider segments such that theweight or area center of all segments in the drain region is closer tothe gate or channel region than to the drain contacts. The currentdivider segments are so positioned in the devices illustrated in FIGS.2-12, 24, and 25. Being closer to the gate or channel region makes iteasier to collect electrons injected from the source side of the deviceduring an ESD event.

[0093] Further, the array or group of small current divider segments indevices 2500 and 2600 are effective for improving performance whetherthe ESD device is formed by a non-silicided or silicided process. In thenon-silicided process, the drain diffusion region already has a highresistance and the array or group of small segments do not substantiallyfurther increase resistance of the ESD current path. However, theincreased depletion region along the periphery of the segments helpsabsorb injected carriers from the forward biased source junction withthe p-substrate 1206 and thereby reduce the current density during anESD event. This effect improves ESD performance of the device.

[0094] Experimentally, a GGNMOS (Ground-Gate NMOS) transistor such asillustrated in FIG. 6 but having six polysilicon gate fingers wasconstructed using 0.45 μm non-silicide CMOS technology. Each gate fingerhad a 0.6 μm gate length, i.e., across the channel between the sourceand drain regions, and 75 μm width. In each drain region there was anarray of field-oxide segments of 0.75 μm by 3 μm, separated from eachother by 3 μm distance, and kept at approximately 0.5 μm from the gateand 1.5 μm from the nearest drain contact. In this structure the draincontact-to-gate spacing was 5 μm, while the source contact-to-gatespacing was 2 μm. It was found that the structure showed consistent HBM(Human-Body-Model) ESD performance of 6.5 KV to over 8 KV, while aconventional structure without the field oxide segments showed widelyfluctuating ESD voltages starting from as low as 1.5 KV.

[0095] The above described experimental device demonstrated superior ESDperformance based on a non-silicided process. It is noted that the widthof each of the parallel field oxide segments (0.75 μm) is less than thespacing (3 μm) between adjacent field oxide segments. The spacingbetween adjacent current divider segments being larger than their widthmeans there was only limited drain resistance increase. The significantESD performance improvement suggests the pseudo-collector effect isespecially significant for this type of structure formed by anon-silicided process. Nevertheless, the structure can also be used insilicided or salicided process.

[0096] Additionally, another advantage of the current divider segmentsis the improved segmentation or partial segmentation effect they provideand the associated increased resistance in the drain region. Whilesegmentation improves ESD performance for general CMOS processtechnology, the increase in drain resistance is particularly beneficialin devices formed by a silicided diffusion process. The current dividersegments serve to segment the N+ drain diffusion region into multiplesmaller parallel-aligned diffusion regions. This substantially segmentsthe MOS transistor device into a number of smaller, aligned MOSprotection transistors. Each of these smaller ESD protection MOStransistors has a drain resistor due to the N+ diffusion regionresistance. When ESD current flows into any of these segmented MOStransistors, the series drain resistance increases the drain voltage inthe corresponding area, thereby forcing the ESD current to also flowinto the other small MOS transistors, which are effectively connected inparallel. This results in the even distribution of the ESD dischargecurrent, which significantly enhances the robustness of the entire MOStransistor. Further, since all the drain resistors are arranged inparallel, the effective total drain resistance is much smaller than thatof each individual segmented region. The effective drain resistancetherefore does not affect the normal effectiveness of the NMOSprotection transistor.

[0097] In some instances, devices including field oxide current dividersegments produced using a salicide process may experience junctionleakage along the junction between the segment and the diffusion region.In device 450 illustrated in FIGS. 4C and 4D, the provision of a layerof polysilicon over the field oxide and extending beyond the edgethereof minimizes the possibility of such leakage.

[0098] Thus, devices constructed according to the present invention willprovide improved ESD protection performance because of one or more ofthe mechanisms described above, depending on the exact layout of eachcurrent divider structure and how much drain resistance increase isassociated with a particular layout and process.

[0099] It is clear from the disclosure that a current divider can be anisland structure of an arbitrary shape. The current dividers block ionimplantation during formation of the source/drain regions, or theemitter/collector regions.

[0100] Further, the formation of source and drain regions can be basedon lightly doped drain (LDD), double diffusion drain (DDD) or anyconventional source/drain formation process and structure. Additionally,a combination of the disclosed structures and a conventional ESD implanttechnique for improving ESD performance can also be practiced within thescope of the present invention.

[0101] While embodiments of an ESD protection device including currentdivider segment formed of polysilicon or field oxide have beendisclosed, the invention is not so limited. ESD protection devicesconsistent with the present invention can include current dividersegments constructed by overlapping polysilicon over part of fieldoxide.

[0102] Embodiments of the present invention can be fabricated with avariety of techniques including salicide, silicide and non-silicideprocesses. Further, ESD protection devices consistent with the presentinvention can be fabricated by process technologies including, forexample, CMOS, NMOS, BiCMOS processes or bipolar processes (without useof polysilicon current divider segments).

[0103] While embodiments of the present invention include formation ofan ESD protection device on a semiconductor substrate, the invention canbe practiced with equal effectiveness using a silicon-on-insulator (SOI)substrate or silicon with implanted oxide layer (SIMOX).

[0104] Other embodiments of the invention will be apparent to thoseskilled in the art from consideration of the specification and practiceof the invention disclosed herein. It is intended that the specificationand examples be considered as exemplary only, with a true scope andspirit of the invention being indicated by the following claims.

We claim:
 1. An electrostatic discharge protection device, comprising: asubstrate; a first diffusion region formed in the substrate; a seconddiffusion region formed in the substrate adjacent to and spaced from thefirst diffusion region; contacts for making a conductive connection tothe first diffusion region; a channel formed in a third region betweenthe first and second diffusion region; and an elongate current dividerextending between the channel and a region of the contacts.
 2. Theprotection device of claim 1, further including a polysilicon gateoverlying the channel.
 3. The protection device of claim 1, furtherincluding a stripe of field oxide overlying the channel.
 4. Theprotection device of claim 1, wherein the substrate comprises a wellregion.
 5. The protection device of claim 1, wherein the substratecomprises a semiconductor layer over an insulator layer.
 6. Theprotection device of claim 1, wherein the current divider has first andsecond ends, the first end being connected to the channel.
 7. Theprotection device of claim 1, wherein the current divider has first andsecond ends, the first end being spaced from the channel.
 8. Theprotection device of claim 1, wherein at least a portion of the currentdivider is disposed at an acute angle relative to the channel.
 9. Theprotection device of claim 1, wherein the current divider is disposedsubstantially perpendicularly to the channel.
 10. The protection deviceof any one of claims 1-9, wherein the current divider is formed of oneof polysilicon, field oxide, and a structure of polysilicon at leastpartially overlapping a field oxide.
 11. The protection device of anyone of claims 1-9, wherein the current divider comprises a field oxidelayer overlayed by a polysilicon layer, a periphery of the polysiliconlayer extending beyond an edge of the field oxide layer.
 12. Theprotection device of claim 1, wherein the substrate comprises asilicon-on-insulator structure.
 13. The protection device of claim 1,wherein the current divider comprises a layer of polysilicon formed overa layer of thin oxide.
 14. The protection device of claim 13, whereinthe substrate comprises a silicon-on-insulator structure.
 15. Theprotection device of claim 1, further including a conductive gateoverlying the channel; wherein the current divider is formed of fieldoxide, one end portion of the current divider partially extendingunderneath the gate.
 16. The protection device of claim 15, wherein theend portion of the current divider is narrower than another portion ofthe current divider.
 17. The protection device of claim 1, furtherincluding a conductive gate overlying the channel; and the currentdivider being formed of field oxide.
 18. The protection device of claim17, wherein an end of the current divider nearest the gate is spacedtherefrom.
 19. The protection device of claim 18, further including aconductive extension member extending from the gate and overlying thenear end of the current divider.
 20. The protection device of claim 15,further including a conductive extension member extending from the gateand overlying at least part of the end portion of the current dividernot partially extending underneath the gate.
 21. The protection deviceof claim 1, further including a polysilicon gate formed over a thinoxide and overlying the channel; and wherein the current dividercomprises a layer of polysilicon formed over a thin oxide, the currentdivider extending from and contiguous with the gate.
 22. The protectiondevice of claim 21, wherein the current divider is substantiallyperpendicular to the gate.
 23. The protection device of claim 1, furtherincluding a stripe of field oxide overlying the channel, the currentdivider being spaced from the field oxide stripe.
 24. The protectiondevice of claim 23, wherein the current divider is formed of fieldoxide.
 25. The protection device of claim 24, wherein the currentdivider includes a layer of polysilicon at least partially overlappingthe field oxide.
 26. The protection device of claim 23, wherein thecurrent divider comprises a layer of polysilicon formed over a thinoxide.
 27. The protection device of claim 1, further including a stripeof field oxide overlying the channel; wherein the current divider isformed of field oxide.
 28. The protection device of claim 27, whereinthe current divider extends from and is contiguous with the field oxidestripe.
 29. The protection device of claim 28, wherein the currentdivider is substantially perpendicular to the field oxide stripe. 30.The protection device of any one of claims 15-21, further including aplurality of the current dividers substantially parallel to each other.31. The protection device of claim 30, wherein each of the plurality ofcurrent dividers is substantially perpendicular to the gate.
 32. Theprotection device of any one of claims 23-28, further including aplurality of the current dividers substantially parallel to each other.33. The protection device of claim 32, wherein each of the plurality ofcurrent dividers is substantially perpendicular to the stripe of fieldoxide.
 34. The protection device of claim 11 further including anelectrical connection to the polysilicon layer.
 35. An electrostaticdischarge protection device, comprising: a substrate; a first diffusionregion formed in the substrate; a second diffusion region formed in aspaced relationship to the first diffusion region; a third diffusionregion formed in the substrate between and spaced from the first andsecond diffusion regions; a first gate overlying a region between thefirst and third diffusion regions; a second gate overlying a regionbetween the second and third diffusion regions; contacts for making aconductive connection to the third diffusion region; a first elongatecurrent divider extending between the first gate and a region of thecontacts; and a second elongate current divider extending between thesecond gate and the region of the contacts.
 36. The protection device ofclaim 35, wherein the substrate comprises a well region.
 37. Theprotection device of claim 35, wherein the substrate comprises asemiconductor layer over an insulator layer.
 38. The protection deviceof claim 35, wherein the first current divider has first and secondends, the first end being connected to the first gate; and the secondcurrent divider having first and second ends, the first end beingconnected to the second gate.
 39. The protection device of claim 35,wherein the first current divider has first and second ends, the firstend being spaced from the first gate; and the second current dividerhaving first and second ends, the first end being spaced from the secondgate.
 40. The protection device of claim 35, wherein the first currentdivider is disposed at an acute angle relative to the first gate; andthe second current divider is disposed at the acute angle relative tothe second gate such that the second current divider is disposedsubstantially symmetrically relative to the first current divider. 41.The protection device of claim 40, wherein the first current divider hasfirst and second ends, the first end being connected to the first gate;and the second current divider having first and second ends, the firstend being connected to the second gate.
 42. The protection device ofclaim 40, wherein the first current divider has first and second ends,the first end being spaced from the first gate; and the second currentdivider having first and second ends, the first end being spaced fromthe second gate.
 43. The protection device of claim 35, wherein thefirst and second current dividers join in the region of the contacts toform a single current divider structure.
 44. The protection device ofclaim 43, wherein an end of the first current divider remote from thesecond current divider is connected to the first gate; and an end of thesecond current divider remote from the first current divider isconnected to the second gate.
 45. The protection device of claim 43,wherein an end of the first current divider remote from the secondcurrent divider is spaced from the first gate; and an end of the secondcurrent divider remote from the first current divider is spaced from thesecond gate.
 46. The protection device of claim 40, wherein the firstand second current dividers are each formed of polysilicon; theprotection device further including a third current divider formed offield oxide and connected between the second ends of the first andsecond current dividers, the third current divider being positionedbetween adjacent contacts in the region of the contacts.
 47. Theprotection device of claim 35, wherein the first current divider isdisposed substantially perpendicularly to the first gate; and the secondcurrent divider is disposed substantially perpendicularly to the secondgate.
 48. The protection device of claim 47, wherein the first currentdivider has first and second ends, the first end being connected to thefirst gate; and the second current divider having first and second ends,the first end being connected to the second gate.
 49. The protectiondevice of claim 47, wherein the first current divider has first andsecond ends, the first end being spaced from the first gate; and thesecond current divider having first and second ends, the first end beingspaced from the second gate.
 50. The protection device of claim 47,wherein the first and second current dividers join in the region of thecontacts to form a single current divider structure.
 51. The protectiondevice of claim 50, wherein an end of the first current divider remotefrom the second current divider is connected to the first gate; and anend of the second current divider remote from the first current divideris connected to the second gate.
 52. The protection device of claim 50,wherein an end of the first current divider remote from the secondcurrent divider is spaced from the first gate; and an end of the secondcurrent divider remote from the first current divider is spaced from thesecond gate.
 53. The protection device of any one of claims 35-45 or47-52, wherein the first and second current dividers are both formed ofone of polysilicon, field oxide, and a structure of polysiliconpartially overlapping field oxide.
 54. The protection device of any oneof claims 35-45 or 47-52, wherein at least one of the first and secondcurrent dividers comprises a field oxide layer.
 55. The protectiondevice of any one of claims 54, wherein a periphery of the polysiliconlayer extends beyond an edge of the field oxide layer.
 56. Theprotection device of claim 47, wherein the first and second currentdividers are each formed of polysilicon; the protection device furtherincluding a third current divider formed of field oxide and connectedbetween the second ends of the first and second current dividers, thethird current divider being positioned between adjacent contacts in theregion of the contacts.
 57. The protection device of claim 43, whereinthe single current divider structures are each formed of field oxide andextend beneath and beyond the first and second gates.
 58. The protectiondevice of claim 43, wherein the single current divider structures areeach formed of field oxide, are substantially parallel to each other,and are skewed relative to the first and second gates.
 59. Theprotection device of claim 43, wherein the single current dividerstructures are each formed of field oxide, are substantially parallel toeach other, respective ends of each of the current divider structuresbeing spaced from the first and second gates, and the single currentdivider structures being substantially perpendicular to the first andsecond gates.
 60. An electrostatic discharge protection device,comprising: a substrate; a first diffusion region formed in thesubstrate; a second diffusion region formed in the substrate adjacent toand spaced from the first diffusion region; contacts for making aconductive connection to the first diffusion region; a channel formed ina third region between the first and second diffusion region; a firstelongate current divider extending between the channel and a region ofthe contacts; and a second elongate current divider adjacent to thefirst divider and extending between the channel and a region of thecontacts.
 61. The protection device of claim 60, further including apolysilicon gate overlying the channel.
 62. The protection device ofclaim 60, further including a stripe of field oxide overlying thechannel.
 63. The protection device of claim 60, wherein the substratecomprises a well region.
 64. The protection device of claim 60, whereinthe substrate comprises a semiconductor layer over an insulator layer.65. The protection device of claim 60, wherein each of the first andsecond current dividers has first and second ends, the first end beingconnected to the channel.
 66. The protection device of claim 60, whereineach of the first and second current dividers has first and second ends,the first end being spaced from the channel.
 67. The protection deviceof claim 60, wherein at least a portion of each of the first and secondcurrent dividers is disposed at an acute angle relative to the channel.68. The protection device of claim 60, wherein each of the first andsecond current dividers is disposed substantially perpendicularly to thechannel.
 69. The protection device of any one of claims 60-68, whereineach of the first and second current dividers is formed of one of thepolysilicon, field oxide, and a structure of polysilicon partiallyoverlapping field oxide.
 70. The protection device of any one of claims60-68, wherein the current divider comprises a field oxide layeroverlayed by a polysilicon layer, a periphery of the polysilicon layerextending beyond an edge of the field oxide layer.
 71. The protectiondevice of any one of claims 70, wherein the current divider comprises afield oxide layer overlayed by a polysilicon layer, a periphery of thepolysilicon layer extending beyond an edge of the field oxide layer. 72.An electrostatic discharge protection device, comprising: a substrate; afirst diffusion region formed in the substrate; a second diffusionregion formed in a spaced relationship to the first diffusion region; athird diffusion region formed in the substrate between and spaced fromthe first and second diffusion regions; a first gate overlying a regionbetween the first and third diffusion regions; a second gate overlying aregion between the second and third diffusion regions; contacts formaking a conductive connection to the third diffusion region; aplurality of adjacent first elongate current dividers extending betweenthe first gate and a region of the contacts; and a plurality of adjacentsecond elongate current dividers extending between the second gate andthe region of the contacts.
 73. The protection device of claim 72,wherein each of the first current dividers has first and second ends,the first ends being connected to the first gate; and each of the secondcurrent dividers having first and second ends, the first ends beingconnected to the second gate.
 74. The protection device of claim 72,wherein each of the first current dividers has first and second ends,the first end being spaced from the first gate; and each of the secondcurrent dividers having first and second ends, the first ends beingspaced from the second gate.
 75. The protection device of claim 72,wherein each of the first current dividers is disposed at an acute anglerelative to the first gate; and each of the second current dividers isdisposed at the acute angle relative to the second gate such that eachof the second current dividers is disposed substantially symmetricallyrelative to a corresponding one of the first current dividers.
 76. Theprotection device of claim 75, wherein each of the first currentdividers has first and second ends, the first ends being connected tothe first gate; and each of the second current dividers having first andsecond ends, the first ends being connected to the second gate.
 77. Theprotection device of claim 75, wherein each of the first currentdividers has first and second ends, the first ends being spaced from thefirst gate; and each of the second current dividers having first andsecond ends, the first ends being spaced from the second gate.
 78. Theprotection device of claim 72, wherein each of the first currentdividers joins a corresponding one of the second current dividers in theregion of the contacts to form a plurality of adjacent single currentdivider structures respectively extending between the first and secondgates.
 79. The protection device of claim 78, wherein an end of each ofthe first current dividers remote from the corresponding second currentdivider is connected to the first gate; and an end of the second currentdivider remote from the corresponding first current divider is connectedto the second gate.
 80. The protection device of claim 78, wherein anend of each of the first current dividers remote from the correspondingsecond current divider is spaced from the first gate; and an end of eachof the second current dividers remote from the corresponding firstcurrent divider is spaced from the second gate.
 81. An electrostaticdischarge (ESD) protection device formed on a first type semiconductorsubstrate, comprising: a gate having a continuous structure located overthe first type semiconductor substrate; a common source region in thefirst type semiconductor substrate on one side of the gate; a pluralityof drain regions in the first type semiconductor substrate located on anopposite side of the gate, wherein the plurality of drain regions areisolated from each other and adjacent to the gate; a plurality ofcontacts distributed over the common source region and the plurality ofdrain regions; a first metal bus over the common source region; aplurality of first contacts connecting the common source region to thefirst metal bus; a second metal bus over the plurality of drain regions;a plurality of second contacts connecting the plurality of drain regionsto the second metal bus.
 82. A semiconductor field-effect transistordevice for electrostatic discharge protection of a semiconductorintegrated circuit device, comprising: a substrate; a gate having anextended stripe-shaped structure formed on the substrate; a drain regionformed in the substrate on a first side of the gate; a source regionformed in the substrate on a second side of the gate; a plurality ofparallel-aligned field oxide islands formed over a surface of thesubstrate, the plurality of field oxide islands originating from thefirst side of the gate and extending underneath the gate withoutextending to the second side of the gate, wherein the plurality of fieldoxide islands divide part of the drain region into an array of parallelcurrent paths and do not divide the source diffusion region.
 83. Anelectrostatic discharge protection device, comprising: a substrate; afirst diffusion region formed in the substrate; a second diffusionregion formed in the substrate adjacent to and spaced from the firstdiffusion region; contacts for making a conductive connection to thefirst diffusion region; a channel formed in a third region between thefirst and second diffusion regions; and a plurality of current dividersegments formed within the first diffusion region, the respectivesegments each formed into one of at least two different shapes, twodifferent sizes, or two different orientations.
 84. The device of claim83, wherein the at least two different shapes are selected from asquare, a circle, a cross shape, a T shape, a V shape, a U shape, and Lshape.
 85. The device of claim 83, wherein the two different shapesdiffer from each other with respect to at least one of length, width,size and cross-sectional area.
 86. The device of claim 83, wherein thelargest dimension of each segment is less than or equal to substantiallysix times a length of the channel.
 87. The device of claim 83, whereinthe plurality of segments are formed of polysilicon segments, fieldoxide segments, or a combination of polysilicon and field oxidesegments.
 88. The device of claim 83, wherein each of the plurality ofsegments has a center-of-area, the respective centers of areas of theplurality of segments being one of aligned or not aligned.
 89. Anelectrostatic discharge protection device, comprising: a substrate; afirst diffusion region formed in the substrate; a second diffusionregion formed in the substrate adjacent to and spaced from the firstdiffusion region; contacts for making a conductive connection to thefirst diffusion region; a channel formed in a third region between thefirst and second diffusion regions; and a plurality of small currentdivider segments formed within the first diffusion region and being oneof evenly and unevenly distributed therein.
 90. The device of 89,wherein a largest dimension of each of the segments is less than orequal to substantially six times a length of the channel.
 91. The deviceof 89, wherein the segments are formed of polysilicon segments, fieldoxide segments, or a combination of polysilicon and field oxidesegments.
 92. An electrostatic discharge protection device, comprising:a substrate; a first diffusion region formed in the substrate; a seconddiffusion region formed in the substrate adjacent to and spaced from thefirst diffusion region; contacts for making a conductive connection tothe first diffusion region; a channel formed in a third region betweenthe first and second diffusion regions; and a plurality of currentdivider segments formed within the first diffusion region and beingunevenly distributed therein.
 93. A method for forming an electrostaticdischarge protection device, comprising the steps of: forming asubstrate; forming a first diffusion region formed in the substrate;forming a second diffusion region in the substrate adjacent to andspaced from the first diffusion region; forming contacts for making aconductive connection to the first diffusion region; forming a channelin a third region between the first and second diffusion region; andforming an elongate current divider extending between the channel and aregion of the contacts.
 94. An electrostatic discharge protectiondevice, comprising: a substrate; a first diffusion region formed in thesubstrate; a second diffusion region formed in the substrate adjacent toand spaced from the first diffusion region; contacts for making aconductive connection to the first diffusion region; a channel formed ina third region between the first and second diffusion regions; aplurality of current divider segments formed within the first diffusionregion and being one of evenly and unevenly distributed therein, atleast one of the segments comprising a field oxide layer overlayed by apolysilicon layer; and a contact formed on the polysilicon layer.
 95. Anelectrostatic discharge protection device, comprising: a substrate; afirst diffusion region formed in the substrate; a second diffusionregion formed in the substrate adjacent to and spaced from the firstdiffusion region; a channel formed in a third region between the firstand second diffusion regions; at least one current divider segmentformed within the first diffusion region, the current divider segmentcomprising a field oxide layer overlapped by a polysilicon layer, and aperiphery of the polysilicon layer extending beyond an edge of the fieldoxide layer.